Most lab testing quietly inflates 2D transistor performance, research reveals

For nearly two decades, two-dimensional (2D) semiconductors have been studied as a complement or possible successor to silicon transistors, promising smaller, faster and more energy-efficient ...
Duke Pratt School of Engineering

Study Finds Next-Generation Transistor Performance Inflated in Most Lab Testing

Duke engineers show how a common device architecture used to test 2D transistors overstates their performance prospects in real-world devices.
IEEE

RRAM Mirrored and RRAM-Transistor Hybrid Single Device Logic Gates Based on Two-Dimensional Materials

Abstract: The unsustainable downscaling of Si transistor run counter to the rapid development of big data. Further geometric sizing needs industrial strategies and promotion. The two-dimensional ...
IEEE

Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis

Abstract: We propose a novel transistor-level synthesis method to minimize the number of transistors needed to implement a digital circuit. In contrast with traditional standard cell design methods or ...