With today's chips packing more power into smaller footprints, getting them from fab to factory now demands a new level of ...

Kurt Sievers, the CEO of Dutch semiconductor giant NXP Semiconductors, who is set to officially step down at the end of ...

Innoscience, a leading Chinese GaN specialist, plans to expand its monthly production of 8-inch (200mm) wafers from 13,000 to ...

SK hynix to reportedly change wafer cutting for its next-gen HBM4 memory and 400-layer NAND flash, as they're becoming ...

Employing more stress testing at the wafer level improves quality while reducing burn-in time and cost. So why isn’t it ...

Defect detection requirements on the order of 10 defective parts per million (DPPM) are driving improvements in inspection ...

The IC final test is directly completed on the entire packaging wafer before the packaging wafer is cut into single die. This complete testing of the whole wafer before dicing can greatly improve the ...

Zero defect in semiconductor packaging is key especially for high demanding reliability applications (automotive, spatial...) combined with high performance technologies (Silicon ultra lowK wafers ...

Applications include IC wafer sort, final test, and test equipment for datacenter/AI GPU/CPU, APU, re-timers, network processors, and high-speed memory products. The MM5625 operates from DC to 20 GHz ...