With today's chips packing more power into smaller footprints, getting them from fab to factory now demands a new level of ...

TSMC's liquid cooling; copper supply risks; EU's new GenAI rules; SIA's state of the industry report; GF acquires MIPS; ...

The operation time of an ideal reliable wafer scanner model is defined at the die level where the actual exposure process takes place as the time unit per die, or at the wafer substrate level as the ...

Innoscience, a leading Chinese GaN specialist, plans to expand its monthly production of 8-inch (200mm) wafers from 13,000 to ...

SK hynix to reportedly change wafer cutting for its next-gen HBM4 memory and 400-layer NAND flash, as they're becoming ...

While Intel, AMD, and Nvidia focus on performance and AI training, IBM doubles down on reliability, cyber defense, and AI ...

Defect detection requirements on the order of 10 defective parts per million (DPPM) are driving improvements in inspection ...

Korean memory chipmaker SK Hynix has adopted the Metron 3D 300 mm in-line wafer metrology system from Infinitesima. SK Hynix will use the technology in volume production as it provides 3D process ...

Nvidia CEO Jensen Huang recently stated that quantum computing is at an inflection point, predicting it will soon solve some ...