EDN

Streamlining the SoC Design Flow

In SoC design, a streamlined verification and analysis flow can contribute significantly to the success of a product. With manufacturing yield and time-to-market schedules crucial, it is important to ...
EDN

Reshaping the SoC power design flow

Power integrity has become one the most critical issues as chip designs have transitioned to 130nm and 90nm processing technologies. Decreasing supply voltages, increasing device density and leakage ...
Design-Reuse

The SoC Leopard Pro Core Compiler from Socle Improves SoC Design Flow Efficiency

Taipei -- Jan. 18, 2006 – Socle, the leading service provider of SoC design platform, enhanced its own design flow technology overall and implemented own developed SoC Leopard Pro Core Compiler ...
Semiconductor Engineering

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...
Nasdaq

Synopsys and Samsung Foundry Announce Reference Flow for Predictable Execution of ASIL D-Compliant SoC Design for Automotive Applications

Samsung Foundry and Synopsys' optimized flow achieves predictable execution of in-system test, implementation, verification, timing and physical signoff for ASIL D-compliant SoC design Includes ...
CIOL

Fujitsu and Synopsys deliver optimized and predictable customized SoC (ASIC) design flow

MOUNTAIN VIEW, USA: Synopsys Inc. announced, through joint collaboration with Fujitsu Semiconductor Ltd, a faster, area-optimized and highly predictable Customized SoC (ASIC) design flow for mutual ...
Design News

EDA Analytics Tool Boosts SoC Design Productivity

Circuit design involves evaluating a number of design scenarios using available data. To deal with the data explosion associated with increasing design complexity, EDA company Synopsys, Inc. has ...
Semiconductor Engineering

Securing IP Integrity In Advanced SoC Design

In today’s complex system-on-chip (SoC) design flows, intellectual property (IP) blocks are everywhere—licensed from third parties, leveraged from internal libraries, or hand-crafted by expert teams.
Electronic Design

SystemC Advances Set the Stage For New SoC Design Flow Strategy

A new specification for Open Core Protocol (OCP) users will present a seamless flow for complex system-on-a-chip (SoC) designs. Publication of the spec comes via the OCP International Partnership (OCP ...
Electronic Design

DDR3 and DDR2 Memory IP Bolsters SoC Designs

A full range of DesignWare DDR intellectual property (IP) is available for systems-on-a-chip (SoCs) that require an interface to high-performance DDR3, DDR2, and DDR memory subsystems. The DesignWare ...